1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate of a liquid crystal display device that has a shorting bar used for testing.
2. Description of Related Art
In general, liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules. Because of their peculiar characteristics, liquid crystal molecules have a definite orientational arrangement that can be controlled by an applied electric field. In other words, when electric fields are applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since incident light is refracted according to the arrangement of the liquid crystal molecules image data can be displayed.
Of the many different types of LCDs, an active matrix LCD (AM-LCD), having thin film transistors and pixel electrodes that are arranged in a matrix, is a major subject of research and development. This is at least partially due to the high resolution and superior ability of AM-LCDs to displaying moving image.
LCD devices are typically light, thin, and consume little power. LCDs have become widely used in office automation (OA) equipment and in video display units.
A typical liquid crystal display (LCD) panel has upper and lower substrates and an interposed liquid crystal layer. The upper substrate, often referred to as a color filter substrate, usually includes a common electrode, color filters, and a black matrix. The lower substrate, often referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes.
As previously indicated the operation of an LCD device is based on the principle that the alignment direction of liquid crystal molecules depends on an applied electric field, such as that produced by the common and pixel electrodes. A liquid crystal layer having a spontaneous polarization characteristic is an optical anisotropy material. Liquid crystal molecules have dipole moments based on the spontaneous polarization when a voltage is applied. Thus, the alignment direction of the liquid crystal molecules is controlled by applying an electric field to the liquid crystal molecules. When the alignment direction of the liquid crystal molecules is properly adjusted, the liquid crystal molecules are aligned, and light is refracted along the alignment direction to display image data. The liquid crystal molecules function as optical modulation elements having predetermined optical characteristics.
FIG. 1 shows the configuration of a typical LCD device. The LCD device 11 includes upper and lower substrates 5 and 22 and an interposed liquid crystal layer 14. The upper and lower substrates 5 and 22 are generally referred to as a color filter substrate and an array substrate, respectively.
On the upper substrate 5, on the surface opposing the lower substrate 22, are a black matrix 6 and a color filter layer 7. The color filter layer 7 includes a plurality of red (R), green (G), and blue (B) color filters formed in the shape of a matrix array. Each color filter is surrounded by the black matrix 6. Also on the upper substrate 5 is a common electrode 18 that covers the color filter layer 7 and the black matrix 6.
On the lower substrate 22, on the surface opposing the upper substrate 5, is a plurality of thin film transistors (TFTs) “T” that act as switching devices. The TFTs are formed in the shape of a matrix array that corresponds to that of the color filter layer 7. A plurality of crossing gate and data lines 13 and 15 are positioned such that each TFT “T” is located near a crossover point of the gate and data lines 13 and 15.
Further on the lower substrate 22 is a plurality of pixel electrodes 17. The pixel electrodes are formed in pixel regions “P” defined by the crossing gate and data lines 13 and 15. The pixel electrodes 17 are usually formed of a transparent conductive material having good transmissivity, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
According to the above-described LCD device, scanning signals are applied to gate electrodes of the TFTs “T” through the gate lines 13, while data signals are applied to source electrodes of the TFTs “T” through the data lines 15. As a result, the liquid crystal molecules of the liquid crystal layer 14 are aligned and orientated by switching the TFTs “T.” By properly switching the TFTs the light that passes through the liquid crystal layer 14 can be controlled so as to produce a desired image.
FIG. 2 is a plan view illustrating several pixels of an array substrate according to the conventional art. As shown, an array substrate includes a plurality of pixel regions “P,” each of which has a thin film transistor (TFT) “T”, a pixel electrode 17 and a storage capacitor “C”. Gate lines 13 are arranged in a transverse direction and data lines 15 are arranged in a longitudinal direction such that pairs of gate and data lines 13 and 15 define the pixel regions “P.” Each TFT “T” includes a gate electrode 26, a source electrode 28, a drain electrode 30 and an active layer (not shown). The gate electrodes 26 extend from the gate lines 13, while the data electrodes 28 extend from the data lines 15. Further, gate pads 41 are arranged respectively at one end of each gate line 13. The gate pads 41 electrically communicate with the gate lines 13. Data pads (not shown) are arranged respectively at one end of each data line 15 (and communicate with the data lines 15). A plurality of transparent pad electrodes is formed on the pads. The transparent pad electrodes receive external signals from driving circuitry (not show). A transparent pad electrode on a gate pad 41 is called a gate pad electrode 43, and a transparent pad electrode on a data pad (not shown) is called a data pad electrode (also not shown).
In general, the gate lines 13 are grouped into odd numbered gate lines 13a and even numbered gate lines 13b, and the data lines 15 are grouped into odd numbered data lines and even numbered gate lines. The gate pads 41 and the data pads (not show) are also correspondingly grouped into even numbered gate/data pads and odd numbered gate/data pads. Among the gate and data lines 13 and 15, the even numbered lines and the odd numbered lines are respectively connected to different shorting bars. The shorting bars prevent discharge of static electricity from occurring on the gate and data lines 13 and 15.
In other words, since transparent glass (an insulator) is conventionally used for the substrates of LCD devices, static electricity generated during the manufacturing processes must be dealt with. Although static electricity typically has only a small electric charge, it has a high voltage that can damage the TFT, the gate and data lines, and the other elements if discharged. To prevent such problems, the shorting bars connected to the gate and data lines 13 and 15 force equipotentials on the electrically connected elements. Namely, each shorting bar is electrically connected with the even/odd numbered gate or data pad. For convenience, the following explanation will focus on the gate shorting bars, but the data shorting bars are similar.
Arrays having the above-mentioned structure are tested for open and shorted gate (and data) lines using special test equipment, such as an In-Process Tester (IPT) from Photon Dynamics, Inc., Milpitas, Calif. That tester can use non-contact methods to find array defects. Further, while testing gate lines 13 for opens and shorts using the IPT, the gate lines 13 are grouped into the odd numbered gate lines 13a and the even numbered gate lines 13b. A voltage is applied to the odd and even numbered gate lines 13a and 13b. 
Still referring to FIG. 2, a first gate shorting bar 31 is formed in the same plane using the same material as the gate lines 13 such that the first gate shorting bar 31 connects to the odd numbered gate lines 13a. A second gate shorting bar 33 is formed along with the data lines 15 in a later manufacturing step. The even numbered gate lines 13b do not contact the first gate shorting bar 31, but are connected with the second gate shorting bar 33 through transparent connectors 37. Namely, portions connecting the even numbered gate lines 13b to the first gate shorting bar 31 are eliminated during fabrication. Therefore, one end of the transparent connectors 37 contacts the end of these portions, while the other end of the transparent connectors 37 contacts the second gate shorting bar 33.
After completing the array substrate and after testing for opens and shorts, the first and second gate shorting bars 31 and 33 are cut away along lines A-B or E-F. However, during cutting, if the gate lines 13 and gate pads 41 are made of copper or of a copper alloy, the gate pads 41 tend to rise from the glass substrate. Namely, since copper and copper alloys do not have good adhesion to glass substrates the gate pads 41 are affected by the physical contact during cutting. Thus, portions of the gate pads 41 and gate lines 13 around the cut lift off of the glass substrate.
Various structures of the above-mentioned array substrate will be explained in more detail with reference to FIGS. 3A to 3D and 4A to 4D. FIGS. 3A to 3D are plan views that help explain the fabricating processes of the array substrate of FIG. 2. FIGS. 4A to 4D are cross-sectional views, taken along lines III—III and IV—IV, of FIGS. 3A to 3D that help explain conventional fabricating processes of an array substrate and a TFT “T.”
Thin film transistors (TFTs) can be divided into two different categories based upon the relative disposition of their gate electrodes, staggered and coplanar. Staggered type TFTs include the inverted staggered type, which is generally used for LCD devices due to their simple structure and superior efficiency. Within the inverted staggered type TFT is a back channel etched type (EB) and an etch stopper type (ES). A manufacturing method of the back channel etched type TFT will be explained hereinafter.
Referring now to FIGS. 3A and 4A, a substrate 22 is first cleaned of organic materials and foreign substances to promote adhesion of a first metal layer that is subsequently deposited on the substrate 22 by sputtering. Then, the first metal layer, i.e., copper (Cu) or copper alloy (Cu-alloy), is patterned to form the gate lines 13, gate electrodes 26 that extend from each gate line, gate pads 41 at one end of the gate lines, and a first shorting bar 31 that is perpendicular to the gate lines 13 and that contact the gate pads 41 through connecting lines 32, 32a and 32b. 
The gate lines 13 are grouped into odd numbered gate lines 13a and even numbered gate lines 13b. Each odd numbered gate line 13a, including its gate pad 41, electrically contacts the first shorting bar 31 via a direct connecting line 32, while each even numbered gate line 13b, including its gate pad 41, electrically contacts the first shorting bar 31 via a first connecting line 32a and a second connecting line 32b. The first connecting lines 32a protrude from the gate pads 41, and the second connecting lines 32b extend from the first shorting bar 32b and perpendicularly contact a first connecting line 32a. 
Still referring to FIGS. 3A and 4A, a gate insulation layer 51 is formed on an entire surface of the substrate 22 and over the patterned first metal layer. Then, a pure amorphous silicon (a-Si:H) layer 52 and a doped amorphous silicon (n+a-Si:H) layer 54 are formed in sequence on the gate insulation layer 51. Thereafter, both the pure amorphous silicon layer 52 and the doped amorphous silicon layer 54 are patterned to respectively form an active layer 53 and an ohmic contact layer 55 on the gate insulation layer 51, particularly over the gate electrode 26.
Now, referring to FIGS. 3B and 4B, a second metal layer is deposited over the substrate. Then, the second metal layer is patterned to form data lines 15 that are perpendicularly to the gate lines 13, a source electrode 28 that extends from each data line, a drain electrode 30 that is spaced apart from each source electrode 28, and a second shorting bar 33 that is spaced apart from the first shorting bar 31 perpendicularly to the gate lines 13. As shown in FIG. 4B, a portion “K” of the ohmic contact layer 55 between the source and drain electrodes 28 and 30 is eliminated using the source and drain electrodes 28 and 30 as masking layers, thereby forming a channel region in the active layer 53 over the gate electrode 26.
Now, referring to FIGS. 3C and 4C, a passivation layer 57 is formed over the remaining portions of the patterned second metal layer such that the passivation layer 57 covers the data lines 15, the source and data electrodes 28 and 30, and the second gate shorting bar 33. Thereafter, the passivation layer 57 is patterned to form drain contact holes 59 to the drain electrodes 30, gate pad contact holes 61 to the gate pads 41, first connecting contact holes 63 to the first connecting line 32a, and second connecting contact holes 65 to the second shorting bar 33. Furthermore, etching holes 67, as shown in FIG. 3C, are formed over each second connecting line 32b when forming the above-mentioned contact holes.
Next, as shown in FIGS. 3D and 4D, a transparent conductive material, such as ITO or IZO, is deposited and patterned to form pixel electrodes 17, each of which contacts a drain electrode 30 through a drain contact hole 59 which is positioned in the pixel region “P” (see FIG. 2). Simultaneously, the gate pad electrodes 43, each of which has an island shape, are formed on the gate pads 41 along with the pixel electrodes 17. The transparent connectors 37 are formed over the first shorting bar 31. Each transparent connector 37 electrically connects each even numbered gate line 13b to the second shorting bar 33 through both the first connecting contact hole 63 and the second connecting contact hole 65.
While patterning the transparent conductive material, the second connecting lines 32b that are exposed by the etching holes 67 (see FIG. 3C) are etched such that the second connecting lines 32b are open-circuited from the first gate shorting bar 31. Accordingly, the even numbered gate lines 13b are not electrically connected with the first shorting bar 31.
In the aforementioned structure, the odd numbered gate lines 13a are connected with the first gate shorting bar 31 and the even numbered gate lines 13b are connected with the second gate shorting bar 33. The gate lines 13 are tested for shorts and opens using the IPT. After testing, the first and second shorting bars 31 and 33 are cut along the lines A-B or E-F. At this time, since the gate lines 13 and gate pads 41 are made of copper (Cu) or copper alloy (Cu-alloy) that does not have good adhesion to the glass substrate 22, the gate lines 13 and gate pads 41 tend to rise from the glass substrate. However, copper (Cu) and copper alloy (Cu-alloy) have good electrical characteristics. Thus, the gate lines 13 and gate pads 41 are affected by the cutting process such that the adhesion between the glass substrate 22 and the gate lines/pads is deteriorated.
FIG. 5 is a cross-sectional view taken along line V—V of FIG. 3D. As shown, a tape carrier package (TCP) 73 having a drive circuit is bonded to the gate pad electrode 43 using an anisotropic conductive film (ACF) 71. However, if the TCP 73 is misaligned with the gate pad electrode 43, or does not contact the gate pad electrode 43 during bonding, the TCP 73 is separated from the ACF 71. Re-work to align the TCP 73 with the gate pad electrode 43 is then required. During re-work, the gate pads 41 and gate lines 13 can be damaged due to the fact that they have low adhesion to the glass substrate 22 caused by the above-mentioned cutting process.